The present disclosure relates to level shift circuits for converting voltage levels of signals, and specifically to a level shift circuit which operates at a low voltage.
FIG. 5 is a circuit diagram illustrating a conventional level shift circuit.
The level shift circuit of FIG. 5 includes two n-type transistors N51, N52, two cross-coupled p-type transistors P51, P52, and a first inverter INV50, wherein the gate and the drain of the p-type transistor P51 are connected to the drain and the gate of the p-type transistor P52, respectively.
The first inverter INV50 inverts an input signal from an input terminal IN, and is powered by a low-voltage source VDD at, for example, 1.5 V. The devices except the first inverter INV50 are high-voltage devices powered by a high-voltage source VDD3 at, for example, 3.3 V. The two n-type transistors N51, N52 have sources coupled to ground, and receive signals complementary to each other. That is, the n-type transistors N51, N52 receive the input signal from the input terminal IN and an inversion signal from the first inverter INV50, respectively, where the inversion signal is obtained by inverting the input signal by the first inverter INV50. The two p-type transistors P51, P52 have sources connected to the high-voltage source VDD3, and gates and drains cross-coupled to each other. The drain of the p-type transistor P51 and the drain of the p-type transistor P52 are connected to the drain of the n-type transistor N51 and the drain of the n-type transistor N52, respectively. An interconnection node between the p-type transistor P51 and the n-type transistor N51 on one side is a node W51, and an interconnection node between the p-type transistor P52 and the n-type transistor N52 on the other side is a node W52. Moreover, an output terminal OUT is connected to the node W52.
Next, operation of the conventional level shift circuit will be described. During stable operation, for example, when the input signal is at a H (VDD) level, and the inversion signal of the input signal is at a L (VSS=0 V) level, the n-type transistor N51 is in an on state, the n-type transistor 52 is in an off state, the p-type transistor P51 is in the off state, and the p-type transistor P52 is in the on state. Moreover, the node W51 which is a node on the one side is at the L (VSS) level, and the node W52 which is a node on the other side is at a H (VDD3) level. Since the n-type transistor N51 and the n-type transistor N52 are complementary to the p-type transistor P51 and the p-type transistor P52, respectively, no current flows during the stable operation.
After that, when the input signal transitions to the L (VSS) level, and state transition occurs, the n-type transistor N51 is turned off, and the n-type transistor N52 is turned on. Thus, a through current flows from the high-voltage source VDD3 to ground via the p-type transistor P52 and the n-type transistor N52 which are in the on state, and the potential at the node W52 starts decreasing from the H (VDD3) level. When the potential at the node W52 decreases to or below a value given by the expression VDD3−Vtp (Vtp is the threshold voltage of the p-type transistor P52), turning on of the p-type transistor P51 is started, so that the potential at the node W51 (potential at the gate of the p-type transistor P52) increases to reduce a drain current of the p-type transistor P52, and the potential at the node W52 further decreases.
Eventually, the potential at the node W51 reaches the H (VDD3) level, and the potential at the node W52 reaches the L (VSS) level, so that the through current no longer flows, and an output logic is inverted, resulting in a stand-by mode for a next transition of the input signal. The case of transition of the input signal from the H level (VDD) to the L level (VSS) has been described, but a similar statement applies to the opposite situation. Converting H-level and L-level signals by the level converter circuit can thus generate H-level and L-level signals having different voltage levels.
Here, assume that the low-voltage source VDD is set to a low voltage close to the threshold voltage of each of the n-type transistors N51, N52 (e.g., 0.7 V).
In general, a drain current of a transistor is proportional to the square of a difference between a gate voltage and a threshold voltage. Thus, drain currents of the n-type transistors N51, N52 exponentially decrease when the low-voltage source VDD is set to decrease in voltage. Assume that the input signal transitions from the H level (VDD) to the L level (VSS). In this case, the drain current of the n-type transistor N52 decreases, whereas the drain current of the p-type transistor P52 does not decrease. This significantly slows that the rate of decrease in the potential at the node W52, so that eventually, delay time that an output signal OUT takes to transition from the H level (VDD3) to the L level (VSS) rapidly increases.
As a measure against the above problem, the gate width of each of the n-type transistors N51, N52 may be increased to obtain high drain currents when the n-type transistors N51, N52 are turned on. However, as previously described, the drain currents of the transistors exponentially decrease when the low-voltage source VDD is set to decrease in voltage, and thus to compensate the decrease, the gate widths have to be significantly increased. This significantly increases the device area, and thus is not practical.
As another measure, the gate width of each of the p-type transistors P51, P52 may be reduced to obtain low drain currents when the p-type transistors P51, P52 are turned on. Assume that the input signal transitions from the H level (VDD) to the level (VSS). In this case, the measure allows the potential at the node W52 to more rapidly decrease, and the increase in delay time that the output signal OUT takes to transition from the H level (VDD3) to the L level (VSS) can be reduced. In contrast to the above case, assume that the input signal transitions from the L level (VSS) to the H level (VDD). In this case, the drain current of the p-type transistor P52 decreases, which increases time required for the potential at the node W52 to increase to the H level (VDD3), so that the delay time that the output signal OUT takes to transition from the L level (VSS) to the H level (VDD3) may be increased.
As described above, in the conventional level shift circuit, it has not been possible to simultaneously reduce both the rising time and the falling time of the potential at the node W52. Signal delay at the output terminal OUT depends on both the rising time and the falling time of the potential at the node W52. Thus, with this circuit configuration, it has been difficult to reduce the increase in delay time in the case of low-voltage setting of the low-voltage source.
Thus, in order to solve the problem arising in the case of the low-voltage setting of the low-voltage source, conventionally, for example, Japanese Patent Publication No. 2001-298356 has proposed a level shift circuit.
The proposed level shift circuit is illustrated in FIG. 6. The level shift circuit is configured to perform precharge control of a node W51 and a node W52, and detects a change in potential from a H level (VDD3) to a L level (VSS) at the node W51 and the node W52.
Specifically, in contrast to the level shift circuit of the FIG. 5, the level shift circuit of FIG. 6 includes an n-type transistor N53 connected between an n-type transistors N51 and ground (VSS), and an n-type transistor N54 connected between an n-type transistors N52 and ground (VSS), wherein instead of cross coupling the gates of p-type transistors P51, P52, the gate of the n-type transistor N53 and the gate of the n-type transistor N54 are respectively connected to the gate of the p-type transistor P51 and the gate of the p-type transistor P52 to perform precharge operation on the nodes W51, W52.
NAND circuits Nand51, Nand52, and inverters INV51, 52 are further disposed. The NAND circuit Nand51 receives output signals from the node W51 and the NAND circuit Nand52, and the NAND circuit Nand52 receives output signals from the node W52 and the NAND circuit Nand51. The inverter INV51 receives the output signal from the NAND circuit Nand51, and an output of the inverter INV51 is connected to the gate of the p-type transistor P51 and the gate of the n-type transistor N53. The inverter INV52 receives the output signal from the NAND circuit Nand52, and an output of the INV52 is connected to the gate of the p-type transistor P52 and the gate of the n-type transistor N54. With this configuration, a decrease in potential at the nodes W51, W52 is detected, and the precharge operation performed on the nodes W51, W52 is controlled.
Moreover, a pull-up resistor R54 set to a high resistance value is connected between the node W51 and the node W52 so that the nodes W51, W52 do not transition to a floating state. Moreover, an output terminal OUT is connected to an output of the NAND circuit Nand52 via an output circuit including an inverter INV53.
In the conventional level shift circuit having a precharge control function, for example, when an input signal is at a H level (VDD), the nodes W51, W52 are both at the H level (VDD3), an output of the NAND circuit Nand51 is at the H level (VDD3), the output of the NAND circuit Nand52 is at the L level (VSS), and the state of an output logic of a latch circuit including the NAND circuits Nand51, Nand52 is held. Moreover, the output of the inverter INV51 is at the L level (VSS), the output of the inverter INV52 is at the H level (VDD3), and the p-type transistor P51 is in an on state and is connected to a high-voltage source VDD3, whereas the n-type transistor N53 is in an off state and is disconnected from ground (VSS), so that the node W51 is precharged to a potential equal to the potential of the high-voltage source VDD3. On the other hand, the p-type transistor P52 is in the off state and is disconnected from the high-voltage source VDD3, whereas the n-type transistor N54 is in the on state and connects the n-type transistor N52 to ground, and the node W52 is pulled up to a high potential of the high-voltage source VDD3 by the p-type transistor P51 in the on state, the pull-up resistor R54, and the n-type transistor N52 in the off state.
From this state, during state transition in which the input signal transitions from the H level (VDD) to the L level (VSS), the n-type transistor N51 is turned off, and the n-type transistor N52 is turned on, so that the node W52 is connected to ground via the n-type transistor N54 in the on state, thereby reducing the potential at the node W52. When the potential at the node W52 decreases below the switching level of the NAND circuit Nand52, the output of the NAND circuit Nand52 is inverted to the H level (VDD3), the output of the NAND circuit Nand51 is also inverted to the L level (VSS), and an output logic of the output terminal OUT is inverted from the H level (VDD3) to the L level (VSS). Further, an output logic of the inverter INV51 is inverted to the H level (VDD3), and an output logic of the inverter INV52 is inverted to the L level (VSS), so that the n-type transistor N54 is turned off and disconnects the node W52 from ground, whereas the p-type transistor P52 is turned on and connects the node W52 to the high-voltage source VDD3. Thus, the node W52 is precharged to a potential equal to the potential of the high-voltage source VDD3. Furthermore, the p-type transistor P51 is turned off, the n-type transistor N53 is turned on, and the node W51, which has been in a precharged state, is pulled up to the high-voltage source VDD3 by the p-type transistor P52 in the on state, the pull-up resistor R54, and the n-type transistor N51 in the off state, thereby resulting in a stand-by mode for a next transition of the input signal.
The case of transition of the input signal from the H level (VDD) to the L level (VSS) has been described, but a similar statement applies to the opposite situation. Thus, converting H-level and L-level signals by the level converter circuit can generate H-level and L-level signals having different voltage levels.
As described above, in the level shift circuit of FIG. 6, the delay of the output terminal OUT depends on the transition from the H level (VDD3) to the L level (VSS) both at the node W51 and at the node W52, but does not depend on the transition from the L level (VSS) to the H level (VDD3) at the node W51 and the node W52. Thus, setting the resistance value of the pull-up resistor R54 to a high value can increase the speed of the transition from the H level (VDD3) to the L level (VSS) at the node W51 and the node W52, so that it is possible to effectively reduce the increase in delay time in the case of the low-voltage setting of the low-voltage source.